This invention relates, in general, to programmable delay circuits, and more particularly to semiconductor capacitance devices.
Fiber channel is an integrated system of specifications for high speed network communication. Communications between network nodes are based on protocol and hardware standards designed for synchronous high speed data transfers at a fixed rate of 1.0625 gigabits per second. A fiber channel network has no system master clock as such so each node provides an oscillator for producing its own transmission timing signals. These localized oscillators are generally crystal controlled and tuned to 106.25 megahertz. Phase shifting circuits produce the bit interval timing signals for sending data at the specified 1.0625 gigabits per second data transmission rate. Because the network transmitters are asynchronous each node also provides its own receiving clock for synchronizing to transmitted data signals. The frequency and phase of the receiving clock are adjusted to align with the incoming data bits so the data is captured when the bit signals are stable and not during logic level transitions when there is a higher probability of data error.
A ring oscillator circuit is used for generating the receiving clock signal because its phase and frequency can be adjusted to synchronize to the data signals. Each stage of the ring oscillator has an array of programmable delay elements which are switched on or off to add or subtract delay for adjusting the clock signal to the data signal.
A conventional programmable delay element consists of a transistor switch in series with a capacitor. When the transistor switch is turned on the capacitor is connected to the stage and provides a capacitive load for slowing it down. When the transistor switch is turned off the capacitor is disconnected from the stage, thereby speeding it up. Parasitic capacitance associated with the programmable delay element is always loading the stage, even when the transistor switch is turned off. This parasitic capacitance reduces both the maximum speed of the stage and the programming range because the switched capacitance comprises a smaller portion of the total capacitance.
A disadvantage of the conventional programmable delay element is that it requires a separate transistor switch for controlling the capacitance, which increases the component count and adds to system cost. Moreover, the transistor switch increases parasitic capacitance, thereby increasing the minimum stage delay and reducing both the programming range and the maximum oscillation frequency of the ring oscillator.
What is needed is a method for providing a programmable delay to a ring oscillator circuit that reduces cost by eliminating the need for a separate transistor switch. It would be a further benefit if the method reduced parasitic capacitance in order to provide a higher capacitance multiplication when the capacitor was enabled.